1. Field of the Invention
This invention relates to computer system input/output and, more particularly, to peripheral transaction handling within an input/output node.
2. Description of the Related Art
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. The I/O devices may be coupled to the processors through an I/O bridge which manages the transfer of information between a peripheral bus connected to the I/O devices and a shared bus connected to the processors. Additionally, the I/O bridge may manage the transfer of information between a system memory and the I/O devices or the system memory and the processors.
Unfortunately, many bus systems suffer from several drawbacks. For example, multiple devices attached to a bus may present a relatively large electrical capacitance to devices driving signals on the bus. In addition, the multiple attach points on a shared bus produce signal reflections at high signal frequencies which reduce signal integrity. As a result, signal frequencies on the bus are generally kept relatively low in order to maintain signal integrity at an acceptable level. The relatively low signal frequencies reduce signal bandwidth, limiting the performance of devices attached to the bus.
Lack of scalability to larger numbers of devices is another disadvantage of shared bus systems. The available bandwidth of a shared bus is substantially fixed (and may decrease if adding additional devices causes a reduction in signal frequencies upon the bus). Once the bandwidth requirements of the devices attached to the bus (either directly or indirectly) exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting access to the bus, and overall performance of the computer system including the shared bus will most likely be reduced. An example of a shared bus used by I/O devices is a peripheral component interconnect (PCI) bus or an extended PCI (PCI-X) bus.
Many I/O bridging devices use a buffering mechanism to buffer a number of pending transactions from the PCI bus to a final destination bus. However buffering may introduce stalls on the PCI bus. Stalls may be caused when a series of transactions are buffered in a queue and awaiting transmission to a destination bus and a stall occurs on the destination bus, which stops forward progress. Then a transaction that will allow those waiting transactions to complete arrives at the queue and is stored behind the other transactions. To break the stall, the transactions in the queue must somehow be reordered to allow the newly arrived transaction to be transmitted ahead of the pending transactions. Thus, to prevent scenarios such as this, the PCI bus specification prescribes a set of reordering rules that govern the handling and ordering of PCI bus transactions.
To overcome some of the drawbacks of a shared bus, some computer systems may use packet-based communications between devices or nodes. In such systems, nodes may communicate with each other by exchanging packets of information. In general, a xe2x80x9cnodexe2x80x9d is a device which is capable of participating in transactions upon an interconnect. For example, the interconnect may be packet-based, and the node may be configured to receive and transmit packets. Generally speaking, a xe2x80x9cpacketxe2x80x9d is a communication between two nodes: an initiating or xe2x80x9csourcexe2x80x9d node which transmits the packet and a destination or xe2x80x9ctargetxe2x80x9d node which receives the packet. When a packet reaches the target node, the target node accepts the information conveyed by the packet and processes the information internally. A node located on a communication path between the source and target nodes may relay or forward the packet from the source node to the target node.
Additionally, there are systems that use a combination of packet-based communications and bus-based communications. For example, a system may connect to a PCI bus and a graphics bus such as AGP. The PCI bus may be connected to a packet bus interface that may then translate PCI bus transactions into packet transactions for transmission on a packet bus. Likewise the graphics bus may be connected to an AGP interface that may translate AGP bus transactions into packet transactions. Each interface may communicate with a host bridge associated with one of the processors or in some cases to another peripheral device.
When PCI devices initiate the transactions, the packet-based transactions may be constrained by the same ordering rules as set forth in the PCI Local Bus specification. The same may be true for packet transactions destined for the PCI bus. These ordering rules are still observed in the packet-based transactions since transaction stalls that may occur at a packet bus interface may cause a deadlock at that packet bus interface. This deadlock may cause further stalls back into the packet bus fabric. In addition, AGP transactions may follow a set of transaction ordering rules to ensure proper delivery of data.
Depending on the configuration of the I/O nodes, transactions may be forwarded through a node to another node either in a direction to the host bridge or away from the host bridge. Alternatively, transactions may be injected into packet traffic at a particular node by a peripheral bus which may be connected locally at that node. In either scenario, a peripheral interface circuit that may buffer and control the peripheral transactions as the transactions are either injected into the communication path or accepted from the communication path may be desirable.
Various embodiments of a peripheral interface circuit for an I/O node of a computer system are disclosed. In one embodiment, a peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit is coupled to receive packet commands from a source such as a receiver. The first buffer circuit may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive the packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. Each of the first and second plurality of buffers is for storing selected packet commands that belong to the respective virtual channel. Each of the plurality of buffers may be illustrative of a FIFO buffer for example. The bus interface circuit is coupled to the first buffer circuit and may be configured to translate the selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus. The bus interface circuit may also be configured to translate the commands suitable for transmission on a peripheral bus into packet commands.
In one particular implementation, the peripheral interface circuit may include a control logic unit coupled to the first buffer circuit and the second buffer circuit. The control logic unit may be configured to control the conveyance of the packet commands to and from the bus interface circuit. Further, the peripheral interface circuit may include a tag logic unit which is also coupled to the first buffer circuit. The tag logic unit may be configured to receive and to generate a tag value for each of the packet commands. The tag value may correspond to the order of receipt of each of the packet commands relative to other packet commands. The peripheral interface circuit may further include an arbitration logic unit which is also coupled to the first buffer circuit and configured to arbitrate between the packet commands stored in the first plurality of buffers depending upon the tag value for each of the control commands.
In another embodiment, a computer system includes one or more processors such as an X86 type processor for example, coupled to one or more input/output nodes via a point-to-point packet bus. The packet bus may be a HyperTransport(trademark) bus for example. The computer system also includes one or more peripheral buses connected to convey address, data and control signals between respective ones of the one or more input/output nodes and one or more peripheral devices. The peripheral bus may be a PCI or PCI-X bus for example. Each of the input/output nodes includes a first transceiver circuit configured to receive a first packet command on a first communication path and a second transceiver circuit configured to receive a second packet command on a second communication path. In addition, the I/O node includes one or more peripheral interface circuits such as the peripheral interface circuit described in the above embodiment.